ajds a écrit:Oui, c'est vrai mais d'un autre coté vu qu'ils sont les seuls à faire ca, je les vois mal expliquer en détail le principe du procédé : c'est la porte ouverte à la copie, même si j'éspère pour eux qu'ils on déposé un brevet la dessus.
Ce qui rends crédible leur discours, c'est que c'est un DAC pro qui s'adresse donc à une clientèle de professionnels avertis (ingénieurs du son, spécialistes en mastering, ect), on est quand même assez loin du marketing bla-bla du grand public. Leurs mesures publiées sont assez explicites et ils invitent leur clients à les reproduire ce qui peut être fait assez facilement dans un monde pro ou les instruments de mesure ne manquent pas.
Dans la liste des clients et des gens qui le recommandent, se trouve entre autres Bob Katz, qui n'est quand même pas n'importe qui.
Que ce soient les seuls à traiter ainsi le jitter j'en suis pas certain, que leur démarche marketing soit originale, je n'en doute pas.
Je ne vois pas trop l'intérêt par rapports aux sytèmes utilisés par les autres DAC pro
par exemple
Apogee :
The subtitle "IntelliDAC" relates to the converter’s unique "intelligent" two-stage re-clocking system, a first for Apogee. Apogee converters have traditionally excelled at removing jitter from the incoming clock signal, but for extremely jittery input sources, more control is needed. The DA-16 solves this problem by utilizing two clocks. A fast-responding 'read' clock, with a wide locking range, fills a dedicated FIFO buffer, while an ultra-low-jitter 'write' clock writes the data out of the buffer, and is used to clock the converters.
The advantage of this configuration is that both incoming clock and data are de-jittered. In addition, the system is less sensitive to phase errors between synchronous digital sources. Errors up to plus or minus 150 degrees can be corrected, substantially reducing the chances of glitching, and enabling the DAC to offer superior performance even when the input signal is extremely unstable.
Par ailleurs
dCS reste très sceptique par rapport à ce genre de traitement asynchrone. Voir leur fort intéressant article, et plus particulièrement p5 :
http://www.dcsltd.co.uk/papers/jitter.pdfIn the absence of a distributed master clock, items in a digital audio chain have to recover
their clocks from the data stream they are fed. They will generally do this by locking a local
phase locked loop (PLL) to the incoming data stream, and to keep data transfers inside the
equipment synchronous, this locked clock is then used internally.
The PLL usually locks to the edges in the incoming data stream, because these are
convenient timing points. The incoming edges will have jitter from their controlling oscillator
(psecs) and additional data jitter – the latter often of several nsecs. The PLL has to filter this
out, which it does by effectively averaging over many incoming edges. The averaging is
performed by making the bandwidth of the oscillator control loop small. For example, a
control loop bandwidth of 1Hz effectively averages over a period of 1/2p seconds. For a PLL
locking to a 48kS/s AES3 data stream, and looking for sync codes (these occur at 96kHz)
averaging is effectively over about 15,000 edges, which will reduce the data jitter by Ö15,000
times (about 124 times) if the spectrum of the jitter is flat.
AES3 at 48 kS/s allows a peak to peak jitter of 80 nsecs on a data edge (it is usually better
than this) which is equivalent to about 13 nsecs rms jitter. Reducing this by 124 times
(above) will drop it to around 110 psecs rms. In practice, things are better than this:
· the spectrum of the jitter is not flat, but is slightly noise shaped, so the averaging works
better than expected, and
· the data jitter is not usually as bad as the spec allows, although long cable runs will
make it bad again.
Use of a FIFO to store incoming data works in exactly the same way, by allowing a very low
bandwidth in the control loop of the PLL used. It does not eliminate jitter – it is just easier to
achieve low control loop bandwidths. Note that for this to offer lower bandwidths than a
conventional analogue PLL, and for the FIFO to operate half full, FIFO depths of 64K or
more are needed.
If this method of synchronising items in a digital audio chain is used (locking to the previous
equipment rather than a distributed master clock), then it becomes important to avoid jitter
build up in the area of a few Hz around the centre frequencies of the various oscillators used
in the chain.
Data Jitter and Asynchronous Sample Rate Converters
Asynchronous sample rate converters can respond to data jitter and process it into the signal,
irrevocably. For this reason they should be used with care, and if they have to be used,
should be used with low data jitter sources with short cable runs.
Fred
), non je ne vais pas resortir du placard le vieux débat "coax vs optique", ou les vieux préjugés du style "le spdif redort directement le signal de la galette sans perte"...
